A REVIEW ON HYBRID MULTIPLIER AND FUNCTIONALITY

Authors

  • Mamta Rani Research Scholar, Department of ECE, IIET

Keywords:

Multiplier, Fractional Product Array

Abstract

This paper discusses the digital system along with its basic functionality. In this paper the discussion has been made on existing researches related to Modified Booth Multipliers With a expected Fractional Product Array, Multiplier Reduction Tree with Logarithmic Logic Depth and Regular connectivity, Multiplication Acceleration Through Twin Precision Magnus, Implementation of a High speed Multiplication on SOC using Twin precision process. The multiplier and their working have been discussed in this paper.

References

Neeta Sharma, Dr. Ravi Sindal “Modified booth multiplier using Wallace structure and efficient carry select adder” in International Journal of Computer Application, ISSN No: 0975-8887, Vol.68-No.13, April-2013, PP. 39-42.

Priya Sharma, Dr. Ravi Sindal “IMPLEMENTATION OF HIGH SPEED AND LOW POWER NOVEL RADIX 2 BOOTH MULTIPLIER USING 2248 BEC CONVERTER” in National Conference On Recent Developments In Electronics (Ncrde 2013), IEEE Delhi Chapter in January, 2013.

K.A.C. Bickerstaff, M. Schulte, and E.E. Swartzlander, Jr., “Reduced Area Multipliers Intl. Conf. on Application-Specific Array Processors, pp. 478-489,1993.

Prasanna Raj P, Rao, Ravi, “VLSI Design and Analysis of Multipliers for Low Power”, Intelligent Information Hiding and Multimedia Signal Processing, Fifth International Conference, pp.: 1354-1357, Sept. 2009.

Jagadeshwar Rao M, Sanjay Dubey,” A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits” IOSR Journal of Electronics and Communication Engineering (IOSRJECE), Volume 3, PP 07-11, Issue 1 (Sep-Oct 2012).

Pouya Asadi, and Keivan Navi, “A new

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Published

2018-09-30

How to Cite

Rani, M. (2018). A REVIEW ON HYBRID MULTIPLIER AND FUNCTIONALITY. Innovative Research Thoughts, 4(6), 32–37. Retrieved from https://irt.shodhsagar.com/index.php/j/article/view/948